- Meta has started testing its first in-house AI training chip to reduce reliance on external suppliers like Nvidia and lower infrastructure costs.
- The chip is part of the Meta Training and Inference Accelerator (MTIA) series and is being manufactured by Taiwan-based TSMC.
Meta has started testing its first in-house chip for training artificial intelligence systems, marking a significant step in its efforts to reduce dependence on external suppliers like Nvidia.
The social media giant has initiated a small-scale deployment of the chip and plans to expand production if the test phase proves successful, according to sources familiar with the matter.
The development is part of Meta’s long-term strategy to lower its AI infrastructure costs. The company has projected its total expenses for 2025 to be between $114 billion and $119 billion, with up to $65 billion allocated for capital expenditures largely driven by AI-related investments.
One source stated that Meta’s training chip is a dedicated accelerator, designed exclusively for AI-specific tasks, making it more power-efficient than traditional GPUs. The chip is being manufactured by Taiwan-based semiconductor giant TSMC.
The test deployment followed the completion of Meta’s first "tape-out" of the chip, a crucial step in silicon development where an initial design is sent to a chip factory. This process typically takes three to six months and costs tens of millions of dollars, with no guarantee of success.
The new training chip is part of the Meta Training and Inference Accelerator (MTIA) series, which has faced previous setbacks. Despite an earlier failed attempt, Meta successfully deployed an MTIA inference chip last year for recommendation systems on Facebook and Instagram.
Meta executives have expressed their ambition to integrate in-house chips for AI training by 2026, initially for recommendation systems before expanding to generative AI products like Meta AI.
While the company remains one of Nvidia’s largest customers, recent industry trends suggest a shift toward optimizing computational efficiency rather than merely scaling up large language models.
Edited by Harshajit Sarmah